library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity OPDECODER is
    port(
        opcode : in std_logic_vector(7 downto 0);
        en_add : out std_logic;
        en_store : out std_logic;
        en_load : out std_logic;
        en_jump : out std_logic;
        en_jneg : out std_logic
    );
end entity OPDECODER;

architecture RTL of OPDECODER is
begin
    process(opcode)
    begin
        case opcode is
            when "00000000" => en_add <= '1'; en_store <= '0'; en_load <= '0'; en_jump <= '0'; en_jneg <= '0';
            when "00000001" => en_add <= '0'; en_store <= '1'; en_load <= '0'; en_jump <= '0'; en_jneg <= '0';
            when "00000010" => en_add <= '0'; en_store <= '0'; en_load <= '1'; en_jump <= '0'; en_jneg <= '0';
            when "00000011" => en_add <= '0'; en_store <= '0'; en_load <= '0'; en_jump <= '1'; en_jneg <= '0';
            when "00000100" => en_add <= '0'; en_store <= '0'; en_load <= '0'; en_jump <= '0'; en_jneg <= '1';
            when others => en_add <= '0'; en_store <= '0'; en_load <= '0'; en_jump <= '0'; en_jneg <= '0';
        end case;
    end process;
end architecture RTL;